View UPD77115AF1-XXX-CN6_467433.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
MOS INTEGRATED CIRCUIT
PD77115, 77115A
16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR
DESCRIPTION
The PD77115 and PD77115A are 16-bit fixed-point digital signal processors (DSP). The PD77115 and PD77115A are RAM based DSP and have the specific circuit for audio application. Unless otherwise specified, the PD77115 refers to PD77115 and 77115A. For details of the functions of the PD77115, refer to the following User's Manuals:
PD77111 Family User's Manual - Architecture PD77016 Family User's Manual - Instructions
: U14623E : U13116E
FEATURES
* * *
Instruction cycle (operating clock) Memory * Internal instruction RAM * Internal data RAM Peripherals * Audio serial interface * Secure Digital (SD) card interface * 16-bit timer * 16-bit host interface * 8-bit port
13.3 ns MIN. (75 MHz MAX.) 11.5K words x 32 bits 16K words x 16 bits x 2 banks
*
Supply voltage * DSP core voltage 2.0 to 2.7 V (MAX. operation speed 50 MHz) 2.3 to 2.7 V (MAX. operation speed 75 MHz) * I/O pin voltage 2.7 to 3.6 V
*
Power consumption
TYP. 50 mW (2.0 V, 50 MHz operation)
ORDERING INFORMATION
Part Number Package 80-pin plastic FBGA (9 x 9) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic FBGA (9 x 9)
PD77115F1-CN6 PD77115GK-9EU PD77115AF1-xxx-CN6
Remark xxx indicates ROM code suffix.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. U14867EJ5V0DS00 (5th edition) Date Published August 2004 NS CP(K) Printed in Japan
The mark
shows major revised points.
2000, 2004
2
X bus Y bus
BLOCK DIAGRAM
Peripheral units Audio serial interface
Data Sheet U14867EJ5V0DS
Data memory unit
X memory data addressing unit
Y memory data addressing unit
R0 to R7
X memory
Y memory
SD card interface
DMA bus
Main bus
Port
Program control unit
Loop control stack
Instruction memory
MAC 16 x 16 + 40 -> 40
ALU(40)
BSFT
Host interface
PC stack
Interrupt control
Operation unit
CPU control
PLL
Timer
PD77115, 77115A
INT1 to INT4
RESET
WAKEUP
CLKOUT
CLKIN
PLL0 to PLL3Note
Note The PLL0 to PLL3 pins are multiplexed with the P4 to P7 pins.
Debug interface
PD77115, 77115A
FUNCTION PIN GROUPS
+ 2.5 V +3V
IVDD Audio Serial Interface
SO SOEN/LRCLK SCK/BCLK SI SIEN/MCLK
EVDD
RESET INT1 to INT4
CLKIN CLKOUT
(4)
Reset, Interrupt Clock
SD Card Interface
SDDAT SDCR SDCLK
WAKEUP
System Control
Port
(8)
P0 to P3,P4/PLL0 to P7/PLL3
(2)
Host Interface
(16)
HCS HA0,HA1 HRD HRE HWR HWE HD0 to HD15
TDO,TICE TCK,TDI,TMS,TRST GND
Debug Interface
(2) (4)
Remark The P4 to P7 pins are multiplexed with PLL0 to PLL3 pins.
Data Sheet U14867EJ5V0DS
3
4
Data Sheet U14867EJ5V0DS
DSP FUNCTION LIST
Item Memory space (words x bits) Int. instruction RAM Int. instruction ROM Data RAM (X/Y memory) Data ROM (X/Y memory) Ext. instruction Ext. data memory (X/Y memory) Instruction cycle (at maximum operating speed) Multiple 15.3 ns (65 MHz) Integer multiple of x1 to 8 (external pin) Peripheral Serial interface 2 channels (speech CODEC) Host interface General-purpose port (I/O programmable) Timer None 1 channel (16-bit resolution) Others Supply voltage - - - DSP core: 2.5 V I/O pins: 3 V Package 100-pin TQFP 80-pin TQFP 80-pin FBGA 100-pin TQFP 80-pin FBGA 100-pin TQFP 80-pin TQFP 80-pin FBGA - - SD card I/F - 2 channels (16-bit resolution) SD card I/F DSP core: 1.5 V I/O pins: 3 V 161-pin FBGA 144-pin LQFP 8-bit bus 4 bits 8 bits 13.3 ns (75 MHz) Integer multiple of x1 to 16 (mask option) Integer multiple of x1 to 16 (external pin) 1 channel (audio CODEC) 16-bit bus 16 bits (some are alternative with host) 2 channels (time-division, audio) 6.25 ns (160 MHz) 32 K x 16 each None 16 K x 16 each None None 8 K x 16 each None 1 M x 16 1 M x 16 (8 K x 16, using SD I/F) 8.33 ns (120 MHz) None 16 K x 16 each 32 K x 16 each None 32 K x 16 each
PD77110
35.5 K x 32 None 24 K x 16 each
PD77111
1 K x 32
PD77112
PD77113A
3.5 K x 32 48 K x 32
PD77114
PD77115,77115A
11.5 K x 32 None 16 K x 16 each
PD77210
31.5 K x 32
PD77213
15.5 K x 32 64K x 32
31.75 K x 32 3 K x 16 each
16 K x 16 each
30 K x 16 each
18 K x 16 each
Integer multiple of x10 to 64 (external pin)
PD77115, 77115A
PD77115, 77115A
PIN CONFIGURATIONS
80-pin plastic fine pitch BGA (9 x 9)
PD77115F1-CN6 PD77115AF1-xxx-CN6
(Bottom View) 9 8 7 6 5 4 3 2 1 J H G F E D C B A A B C D E F G H J (Top View)
Index mark
Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2
Pin Name EVDD NC EVDD IVDD INT2 RESET TDI I.C. I.C. NC SI SDCR GND WAKEUP INT1 TMS TCK I.C. SIEN/MCLK SCK/BCLK
Pin No. C3 C4 C5 C6 C7 C8 C9 D1 D2 D3 D4 D5 D6 D7 D8 D9 E1 E2 E3 E4
Pin Name SDDAT GND INT3 TRST TICE TDO HA0 SOEN/LRCLK P5/PLL1 SO P7/PLL3 SDCLK INT4 IVDD HA1 GND P6/PLL2 P4/PLL0 GND P2
Pin No. E6 E7 E8 E9 F1 F2 F3 F4 F5 F6 F7 F8 F9 G1 G2 G3 G4 G5 G6 G7
Pin Name GND HWR EVDD CLKOUT EVDD P0 P3 HD9 HD4 HRD HWE CLKIN HCS P1 HD15 HD14 HD11 HD8 HD5 HD1
Pin No. G8 G9 H1 H2 H3 H4 H5 H6 H7 H8 H9 J1 J2 J3 J4 J5 J6 J7 J8 J9
Pin Name HRE EVDD GND EVDD HD12 EVDD GND HD2 IVDD HD0 GND NC GND HD13 HD10 HD7 HD6 HD3 GND I.C.
Data Sheet U14867EJ5V0DS
5
PD77115, 77115A
80-pin plastic TQFP (fine pitch) (12 x 12) (Top view)
PD77115GK-9EU
EVDD SDDAT NC WAKEUP INT1 INT2 INT3 INT4 RESET TRST TMS TDI I.C. SDCLK GND IVDD
SDCR GND EVDD
80 79 78
77 76 75 74 73
72 71 70 69
SI NC SIEN/MCLK SCK/BCLK SO SOEN/LRCLK P7/PLL3 GND P6/PLL2 P5/PLL1 P4/PLL0 EVDD P3 P2 P1 P0 HD15 GND NC HD14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
68 67 66 65 64 63 62 61
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
TCK
TICE I.C. I.C. TDO HA1 HA0 GND IVDD GND EVDD CLKIN CLKOUT HWR HRD HCS HWE HRE EVDD GND HD0
21 22
23 24 25 26 27
28 29 30 31
32 33 34 35 36 37 38 39 HD3 HD2 IVDD
EVDD GND HD13
HD12 HD11 HD10 HD9 HD8 HD7 EVDD
GND HD6 HD5 HD4
6
Data Sheet U14867EJ5V0DS
GND I.C. HD1
40
PD77115, 77115A
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name SI NC SIEN/MCLK SCK/BCLK SO SOEN/LRCLK P7/PLL3 GND P6/PLL2 P5/PLL1 P4/PLL0 EVDD P3 P2 P1 P0 HD15 GND NC HD14 Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name EVDD GND HD13 HD12 HD11 HD10 HD9 HD8 HD7 EVDD GND HD6 HD5 HD4 HD3 HD2 IVDD GND I.C. HD1 Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin Name HD0 GND EVDD HRE HWE HCS HRD HWR CLKOUT CLKIN EVDD GND IVDD GND HA0 HA1 TDO I.C. I.C. TICE Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Name TCK I.C. TDI TMS TRST RESET INT4 INT3 INT2 INT1 WAKEUP IVDD GND SDCLK EVDD GND SDCR NC SDDAT EVDD
Data Sheet U14867EJ5V0DS
7
PD77115, 77115A
PIN NAME
CLKIN CLKOUT EVDD GND HA0, HA1 HCS HD0 to HD15 HRD HRE HWE HWR I.C. INT1 to INT4 IVDD NC P0 to P3 RESET SCK/BCLK SDCLK SDCR SDDAT SI SIEN/MCLK SO SOEN/LRCLK TCK TDI TDO TICE TMS TRST WAKEUP : Clock Input : Clock Output : Power Supply for I/O Pins : Ground : Host Data Access : Host Chip Select : Host Data Bus : Host Read : Host Read Enable : Host Write Enable : Host Write : Internally Connected : Interrupt : Power Supply for DSP Core : Non-Connection : Port : Reset : Serial Clock Input/ Output : SD Card Clock Output : SD Card Command Output/ Response Input : SD Card Data Input/ Output : Serial Data Input : Serial Input Enable/ Master Clock Input : Serial Data Output : Serial Output Enable/ Left Right Clock Input/ Output : Test Clock Input : Test Data Input : Test Data Output : Test In-Circuit Emulator : Test Mode Select : Test Reset : Wakeup from STOP Mode
P4/PLL0 to P7/PLL3 : Port/ PLL Setting Input
8
Data Sheet U14867EJ5V0DS
PD77115, 77115A
CONTENTS 1. PIN FUNCTION................................................................................................................................. 1.1 Pin Function Description ......................................................................................................... 1.2 Connection of Unused Pins ..................................................................................................... 2. FUNCTION OUTLINE....................................................................................................................... 2.1 Program Control Unit ............................................................................................................... 2.2 Arithmetic Unit .......................................................................................................................... 2.3 Data Memory Unit ..................................................................................................................... 2.4 Peripheral Unit .......................................................................................................................... 3. RESET FUNCTION........................................................................................................................... 3.1 Hardware Reset......................................................................................................................... 3.2 Initializing PLL........................................................................................................................... 4. FUNCTIONS OF BOOT-UP ROM .................................................................................................. 4.1 Boot at Reset............................................................................................................................. 4.2 Reboot........................................................................................................................................ 4.3 Signature Operation ................................................................................................................. 5. STANDBY MODES........................................................................................................................... 5.1 HALT Mode ................................................................................................................................ 5.2 STOP Mode ................................................................................................................................ 6. MEMORY MAP ................................................................................................................................. 6.1 Instruction Memory................................................................................................................... 6.2 Data Memory ............................................................................................................................. 7. INSTRUCTIONS ................................................................................................................................ 7.1 Outline of Instructions.............................................................................................................. 7.2 Instruction Set and Operation ................................................................................................. 8. ELECTRICAL SPECIFICATIONS .................................................................................................... 9. PACKAGES ....................................................................................................................................... 10. RECOMMENDED SOLDERING CONDITIONS................................................................................ 10 10 14 15 15 16 17 17 18 18 18 18 18 19 19 20 20 20 21 21 23 25 25 26 32 51 53
Data Sheet U14867EJ5V0DS
9
PD77115, 77115A
1. PIN FUNCTION
Because the pin numbers differ depending on the package, refer to the diagram of the package to be used.
1.1 Pin Function Description
* Power supply
Pin No. Pin Name 80-pin FBGA IVDD EVDD A4,D7,H7 A1,A3,E8,F1, G9,H2,H4 GND B4,C4,D9,E3, E6,H1,H5,H9, J2,J8 80-pin TQFP 37,53,72 12,21,30,43,51, 75,80 8,18,22,31, 38,42,52,54, 73,76 - Ground - - - Power to DSP core (+2.5 V) Power to I/O pins (+3 V) - - I/O Function Shared by:
* System control
Pin No. Pin Name 80-pin FBGA CLKIN CLKOUT F8 E9 80-pin TQFP 50 49 11,10,9,7 Input Output Input System clock input Internal system clock output PLL multiple rate setting pin PLL3 to PLL0: 0000 : x16, 0001 : x1, 0010 : x2, 0011 : x3, 0100 : x4, 1000 : x8, 1111 : x15 RESET WAKEUP A6 B5 66 71 Input Input Internal system reset signal input Stop mode release signal input. * When this pin is asserted active, the stop mode is released. - - 0101 : x5, 0110 : x6, 0111 : x7, 1001 : x9, 1010 : x10, 1011 : x11, - - P4 to P7 I/O Function Shared by:
PLL0 to PLL3 E2,D2,E1,D4
1100 : x12, 1101 : x13, 1110 : x14,
* Interrupt
Pin No. Pin Name 80-pin FBGA INT1 to INT4 B6,A5,C5,D6 80-pin TQFP 70,69,68,67 Input External maskable interrupt input. * Detected at the falling edge. - I/O Function Shared by:
10
Data Sheet U14867EJ5V0DS
PD77115, 77115A
* Serial interface
Pin No. Pin Name 80-pin FBGA SCK/BCLK C2 4 80-pin TQFP I/O Serial clock input/output SCK : Standard serial interface(input) BCLK : Audio serial interface(I/O) SOEN/LRCLK D1 6 I/O Serial output enable / Left Right clock input/output SOEN : Standard serial interface(input) LRCLK : Audio serial interface(I/O) SO D3 5 Output (3S) SIEN/MCLK C1 3 Input Serial input enable / Master clock input SIEN : Standard serial interface MCLK : Audio serial interface (Master clock input when master mode) SI B2 1 Input Serial data input - - Serial data output - - - I/O Function Shared by:
Remark The pins marked "3S" under the heading "I/O" go into a high-impedance state on completion of data transfer and input of the hardware reset (RESET) signal. * SD card interface
Pin No. Pin Name 80-pin FBGA SDCLK SDCR D5 B3 80-pin TQFP 74 77 Output I/O (3S) SD card clock output SD card command/response Input : Response Output : Command *Leave pulled up. SDDAT C3 79 I/O (3S) SD card data input/output Input : Read data Output : Write data *Leave pulled up. - - - I/O Function Shared by:
Remark The pins marked "3S" under the heading "I/O" go into a high-impedance state when the SD card interface is not being accessed.
Data Sheet U14867EJ5V0DS
11
PD77115, 77115A
* Host interface
Pin No. Pin Name 80-pin FBGA HA1 D8 80-pin TQFP 56 Input Specifies the register to be accessed by HD15 to HD0. * * 1: Accesses the host interface status register (HST). 0: Accesses the host transmit data register (HDT (out)) when read (HRD = 0), and host receive data register (HDT (in)) when written (HWR = 0). HA0 C9 55 Input Specifies the register to be accessed by HD15 to HD0. * * 1: Accesses bits 15 to 8 of HST, HDT (in), and HDT (out). 0: Accesses bits 7 to 0 of HST, HDT (in), and HDT (out). When 8-bit mode, this signal becomes valid. When 16-bit mode, this signal becomes invalid. HCS HRD HWR HRE HWE HD0 to HD15 F9 F6 E7 G8 F7 H8,G7,H6,J7, F5,G6,J6,J5, G5,F4,J4,G4, H3,J3,G3,G2 46 47 48 44 45 41,40,36,35, 34,33,32,29, 28,27,26,25, 24,23,20,17 Input Input Input Output Output I/O (3S) Chip select input Host read input Host write input Host read enable output Host write enable output 16-bit host data bus - - - - - - - - I/O Function Shared by:
Remark The pins marked "3S" under the heading "I/O" go into a high-impedance state when the host interface is not being accessed. * I/O ports
Pin No. Pin Name 80-pin FBGA P0 P1 P2 P3 P4 P5 P6 P7 F2 G1 E4 F3 E2 D2 E1 D4 80-pin TQFP 16 15 14 13 11 10 9 7 I/O I/O I/O I/O I/O I/O I/O I/O General-purpose I/O port - - - - PLL0 PLL1 PLL2 PLL3 I/O Function Shared by:
12
Data Sheet U14867EJ5V0DS
PD77115, 77115A
* Debugging interface
Pin No. Pin Name 80-pin FBGA TDO TICE TCK TDI TMS TRST C8 C7 B8 A7 B7 C6 80-pin TQFP 57 60 61 63 64 65 Output Output Input Input Input Input For debugging - - - - - - I/O Function Shared by:
* Others
Pin No. Pin Name 80-pin FBGA I.C. A8,A9,B9,J9 80-pin TQFP 39,58,59,62 - - Internally connected. Leave this pin unconnected. NC A2,B1,J1 2,19,78 No-connect pins. Leave these pins unconnected. - - I/O Function Shared by:
Caution If any signal is input to these pins or if an attempt is made to read these pins, the normal operation of the PD77115 is not guaranteed.
Data Sheet U14867EJ5V0DS
13
PD77115, 77115A
1.2 Connection of Unused Pins
1.2.1 Connection of function pins When mounting, connect unused pins as follows:
Pin INT1 to INT4 SCK/BCLK SI SIEN/MCLK SOEN/LRCLK SO SDCLK SDCR SDDAT HA0, HA1 HCS, HRD, HWR HRE, HWE HD0 to HD15 P0 to P3 TCK TDO, TICE TMS, TDI TRST CLKOUT WAKEUP
Note
I/O Input I/O Input Input I/O Output Output I/O I/O Input Input Output I/O I/O Input Output Input Input Output Input Connect to EVDD or GND. Connect to EVDD. Leave unconnected. Leave unconnected Connect to GND. Connect to EVDD. Connect to EVDD or GND.
Recommended Connection
Connect to EVDD via pull-up resistor, or connect to GND via pull-down resistor.
Connect to EVDD via pull-up resistor, or connect to GND via pull-down resistor.
Connect to GND via pull-down resistor. Leave unconnected. Leave unconnected. (internally pulled up). Leave unconnected. (internally pulled down). Leave unconnected. Connect to EVDD.
Note
These pins may be left unconnected if HCS, HRD, and HWR are fixed to the high level. However, connect these pins as recommended in the halt and stop modes when the power consumption must be lowered.
1.2.2 Connection of no-function pins
Pin I.C. NC I/O - - Leave unconnected. Leave unconnected. Recommended Connection
14
Data Sheet U14867EJ5V0DS
PD77115, 77115A
2. FUNCTION OUTLINE 2.1 Program Control Unit
This unit is used to execute instructions, and control branching, loops, interrupts, the clock, and the standby mode of the DSP. 2.1.1 CPU control A three-stage pipeline architecture is employed and almost all the instructions, except some instructions such as branch instructions, are executed in one system clock. 2.1.2 Interrupt control Interrupt requests input from external pins (INT1 to INT4) or generated by the internal peripherals (serial interface and host interface) are serviced. The interrupt of each interrupt source can be enabled or disabled. Multiple interrupts are also supported. 2.1.3 Loop control task A loop function without any hardware overhead is provided. A loop stack with four levels is provided to support multiple loops. 2.1.4 PC stack A 15-level PC stack that stores the program counter supports multiple interrupts and subroutine calls. 2.1.5 PLL A PLL is provided as a clock generator that can multiply an external clock input to supply an operating clock to the DSP. A multiple of x1 to x16 can be set by pins(PLL0 to PLL3). Two standby modes are available for lowering the power consumption while the DSP is not in use. * HALT mode : Set by execution of the HALT instruction. The current consumption drops to several mA. The normal operation mode is recovered by an interrupt or hardware reset. * STOP mode : Set by execution of the STOP instruction. The current consumption drops to several 10 A. The normal operation mode is recovered by hardware reset or WAKEUP pin. 2.1.6 Instruction memory 64 words of the instruction RAM are allocated to interrupt vectors. A boot-up ROM that boots up the instruction RAM is provided, and the instruction RAM can be initialized or rewritten by host boot (boot via host interface). The PD77115 has 11.5K-word instruction RAM.
Data Sheet U14867EJ5V0DS
15
PD77115, 77115A
2.2 Arithmetic Unit
This unit performs multiplication, addition, logical operations, and shift, and consists of a 40-bit multiply accumulator, 40-bit data ALU, 40-bit barrel shifter, and eight 40-bit general-purpose registers. 2.2.1 General-purpose registers (R0 to R7) These eight 40-bit registers are used to input/output data for arithmetic operations, and load or store data from/to data memory. A general-purpose register (R0 to R7) is made up of three parts: R0L to R7L (bits 15 to 0), R0H to R7H (bits 31 to 16), and R0E to R7E (bits 39 to 32). Depending on the type of operation, RnL, RnH, and RnE are used as one register or in different combinations. 2.2.2 Multiply accumulator (MAC) The MAC multiplies two 16-bit values, and adds or subtracts the multiplication result from one 40-bit value, and outputs a 40-bit value. The MAC is provided with a shifter (MSFT: MAC ShiFTer) at the stage preceding the input stage. This shifter can arithmetically shift the 40-bit value to be added to or subtracted from the multiplication result 1 or 16 bits to the right . 2.2.3 Arithmetic logic unit (ALU) This unit inputs one or two 40-bit values, executes an arithmetic or logical operation, and outputs a 40-bit value. 2.2.4 Barrel shifter (BSFT: Barrel ShiFTer) The barrel shifter inputs a 40-bit value, shifts it to the left or right by any number of bits, and outputs a 40-bit value. The data may be arithmetically shifted to the right shifted to the right, in which case the data is sign-extended, or logically shifted to the right, in which case 0 is inserted from the MSB.
16
Data Sheet U14867EJ5V0DS
PD77115, 77115A
2.3 Data Memory Unit
The data memory unit consists of two banks of data memory and two data addressing units. 2.3.1 Data memory The DSP have two banks of data memory (X data memory and Y data memory). A 64-word peripheral area is assigned in the data memory space. The PD77115 has 16K words x 2 banks data RAM. 2.3.2 Data addressing unit An independent data addressing unit is provided for each of the X data memory and Y data memory spaces. Each data addressing unit has four data pointers (DPn), four index registers (DNn), one modulo register (DMX or DMY), and an address ALU.
2.4 Peripheral Unit
A serial interface, host interface, general-purpose I/O port, and wait cycle register are provided. All these internal peripherals are mapped to the X data memory and Y data memory spaces, and are accessed from program as memory-mapped I/Os. 2.4.1 Audio Serial interface (ASIO) One serial interface is provided. This serial interface has two mode which are the audio serial and the standard serial. The standard serial is compatible other PD77111 family DSP. The audio serial interfaces have the following features: * Mode : Master mode or Slave mode Master mode : MCLK (input), BCLK (output), LRCLK (output), support 256 fs, 384 fs and 512 fs Slave mode : MCLK (unused), BCLK (input), LRCLK (input) * Frame format : 32 or 64 bits audio format (LRCLK format), MSB first input/output. * Handshake : Handshaking with the external devices is implemented with a dedicated frame signal (LRCLK). Handshaking with the internal units, polling, wait, or interrupt are used. The standard serial interfaces have the following features: * Serial clock * Frame length * Handshake : Supplied from external source to each interface. The same clock is used for input and output on the interface. : 8 or 16 bits, and MSB or LSB first selectable for each input or output : Handshaking with external devices is implemented with a dedicated status signal. With the internal units, polling, wait, or interrupt are used. 2.4.2 Host interface (HIO) This is an 16-bit parallel port that inputs data from or outputs data to an external host CPU or DMA controller. In the DSP, a 16-bit register is mapped to memory for input data, output data, and status. Handshaking with an external device is implemented by using a dedicated status signal or a dedicated status register. Handshaking with internal units is achieved by means of polling, wait, or interrupts.
Data Sheet U14867EJ5V0DS
17
PD77115, 77115A
2.4.3 General-purpose I/O port (PIO) This is a 8-bit I/O port that can be set in the input or output mode in 1-bit units. 2.4.4 SD card interface (SDCIF) This interface is for access SD card. It supports the DMA transfer for input data to internal data RAM. The SD card is accessed by using a dedicated routine of system ROM. 2.4.5 Timer This is 16-bit timer unit. The count source can be selected from system clock, SD card clock, serial clock and INT4 input. Timer unit generates interrupt for interface internal units.
3. RESET FUNCTION
When a low level of a specified width is input to the RESET pin, the device is initialized.
3.1 Hardware Reset
If the RESET pin is asserted active (low level) for a specified period, the internal circuitry of the DSP is initialized. If the RESET pin is then deasserted inactive (high level), boot processing of the instruction RAM is performed according to the status of the port pins (P0 and P1). After boot processing, processing is executed starting from the instruction at address 0x200 of instruction memory (reset entry). No power-ON reset function is available.
3.2 Initializing PLL
Initializing the PLL starts during boot up program at reset. The pins (PLL0 to PLL3) that specify the PLL multiple rate must be kept stable for the duration of 3 clocks before and for the duration of 50 clocks after reset has been cleared (the clock is input from CLKIN). It takes the PLL 100 s to be locked. Until the PLL is lacked, the DSP internal is operated by the CLKIN clock. To use the PLL clock as an internal operating clock, set the clock control register (internal peripheral) by user program.
4. FUNCTIONS OF BOOT-UP ROM
To rewrite the contents of the instruction memory on power application or from program, boot up the instruction RAM by using the internal boot-up ROM. The PD77115 has a function to verify the contents of the internal instruction RAM.
4.1 Boot at Reset
After hardware reset has been cleared, the boot program first reads the general-purpose I/O ports P0 and P1 and, depending on their bit pattern, determines the boot mode (host boot or non boot). After boot processing, processing is executed starting from the instruction at address 0x200 (reset entry) of the instruction memory. The pins (P0 and P1) that specify the boot mode must be kept stable for the duration of 3 clocks before and for the duration of 12 clocks after reset has been cleared (the clock is input from CLKIN).
18
Data Sheet U14867EJ5V0DS
PD77115, 77115A
P1 0 0 1 1
P0 0 1 0 1
Boot Mode Does not execute boot but branches to address 0x200
Note
.
Executes host byte boot and then branches to address 0x200. Setting prohibited Executes host word boot and then branches to address 0x200.
Note This setting is used when the DSP must be reset to recover from the standby mode after reset boot has been executed once. A boot parameter and instruction code are obtained via the host interface, and transferred to the instruction RAM. The data transfer support byte mode and word mode.
4.2 Reboot
By calling the reboot entry address from the program, the contents of the instruction RAM can be rewritten. An instruction code is obtained via the host interface and transferred to the instruction RAM. The data transfer support byte mode and word mode. The entry address is 0x6. Host reboot is executed by calling this address after setting the following parameter: * R7L : Number of instruction steps for rebooting * DP3 : First address of instruction memory to be loaded
4.3 Signature Operation
The PD77115 has a signature operation function so that the contents of the internal instruction RAM can be verified. The signature operation performs a specific arithmetic operation on the data in the instruction RAM booted up, and returns the result to a register. Perform the signature operation in advance on the device when it is operating normally, and repeat the signature operation later to check whether the data in RAM is correct by comparing the operation result with the previous result. If the results are identical, there is no problem. The entry address is 0x9. Execute the operation by calling this address after setting the following parameter. The operation result is stored in register R7. * R7L: Number of instruction steps for operation * DP3: First address of instruction memory for operation
Data Sheet U14867EJ5V0DS
19
PD77115, 77115A
5. STANDBY MODES
Two standby modes are available. By executing the corresponding instruction, each mode is set and the power consumption can be reduced.
5.1 HALT Mode
To set this mode, execute the HALT instruction. In this mode, functions other than clock circuit and PLL are stopped to reduce the current consumption. To release the HALT mode, use an interrupt or hardware reset. When releasing the HALT mode using an interrupt, the contents of the internal registers and memory are retained. It takes several 10 system clocks to release the HALT mode when the HALT mode is released using an interrupt. In the HALT Mode, the clock circuit of the PD77115 supplies the following clock as the internal system clock. The clock output from the CLKOUT pin is also as follows. The clock output from the CLKOUT pin, however, has a high-level width that is equivalent to 1 cycle of the normal operation (i.e., the duty factor is not 50%). * PD77115: 1/l of internal system clock (l = integer from 1 to 16, specified by register)
5.2 STOP Mode
To set the STOP mode, execute the STOP instruction. In the STOP mode, all the functions, including the clock circuit and PLL, can be stopped and the power consumption is minimized with only leakage current flowing. To release the STOP mode, use hardware reset or WAKEUP pin. When releasing the STOP mode by using the WAKEUP pin, the contents of the internal registers and memory are retained, but it takes several 100 s to release the mode.
20
Data Sheet U14867EJ5V0DS
PD77115, 77115A
6. MEMORY MAP
A Harvard architecture, in which the instruction memory space and data memory space are separated is employed.
6.1 Instruction Memory
6.1.1 Instruction memory map
0xFFFF
System
0xA000 0x9FFF Instruction RAM (8K words)
0x8000 0x7FFF System 0x1000 0x0FFF Instruction RAM (3.5K words) 0x0240 0x023F Vector area (64 words) 0x0200 0x01FF Boot-up ROM (512 words) 0x0000
Caution Programs and data cannot be placed at addresses reserved for the system, nor can these addresses be accessed. If these addresses are accessed, the normal operation of the device cannot be guaranteed.
Data Sheet U14867EJ5V0DS
21
PD77115, 77115A
6.1.2 Interrupt vector table Addresses 0x200 to 0x23F of the instruction memory are entry points (vectors) of interrupts. Four instruction addresses are assigned to each interrupt source.
Vector 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C INT1 INT2 INT3 INT4 SI input SO output SDDAT input / PBU SDDAT output HI input HO output SDCR input Timer Reset Reserved Interrupt Source
Cautions
1. Although reset is not an interrupt, it is handled like an interrupt as an entry to a vector. 2. It is recommended that unused interrupt source vectors be used to branch an error processing routine.
22
Data Sheet U14867EJ5V0DS
PD77115, 77115A
6.2 Data Memory
6.2.1 Data memory map
0xFFFF
System
0x6000 0x5FFF Data RAM (8K words)
0x4000 0x3FFF System 0x3840 0x383F 0x3800 Peripheral (64 words) 0x37FF System 0x3000 0x2FFF Data RAM (4K words) 0x2000 0x1FFF System 0x1000 0x0FFF Data RAM (4K words) 0x0000
Caution Programs and data cannot be placed at addresses reserved for the system, nor can these addresses be accessed. If these addresses are accessed, the normal operation of the device cannot be guaranteed.
Data Sheet U14867EJ5V0DS
23
PD77115, 77115A
6.2.2 Internal peripherals The internal peripherals are mapped to the internal data memory space.
X/Y Memory Address 0x3800 0x3801 0x3802 0x3803 0x3804 0x3805 0x3806 0x3807 0x3808 to 0x380F 0x3810 0x3811 0x3812 0x3813 0x3814 0x3815 0x3816 0x3817 to 0x381F 0x3820 0x3821 0x3822 0x3823 0x3824 to 0x382D 0x382E 0x382F 0x3830 0x3831 0x3832 0x3833 0x3834 to 0x383F Register Name SDT/ASDT SST ASST Reserved area PDT PCD HDT HST Reserved area SDDR SDCMD_IDX SDCMD_AGH SDCMD_AGL SDCTL SDRPR SDSBR Reserved area TIR TCR TCSR TENR Reserved area CLKCNTL Reserved area PSAR PSR PRR PCR Reserved area Serial data register Serial status register Audio serial status register Caution Do not access this area. Port data register Port command register Host data register Host status register Caution Do not access this area. SD card data register SD card command register index SD card command register argument high SD card command register argument low SD card control register SD card response register SD card CRC status busy register Caution Do not access this area. Timer initialize value register Timer count register Timer control / status register Timer count enable register Caution Do not access this area. Clock control register Caution Do not access this area. DMA start address register DMA size register DMA pointer register DMA control register Caution Do not access this area. - - PLL - SDCIF - Timer - SDCIF HIO - PIO Function Peripheral Name ASIO
Cautions
1. The register names listed in this table are not reserved words of the assembler or the C language. Therefore, when using these names in assembler or C, the user must define them. 2. The same register is accessed, as long as the address is the same, regardless of whether the X memory space or Y memory space is accessed. 3. Even different registers cannot be accessed at the same time from both the X and Y memory spaces.
24
Data Sheet U14867EJ5V0DS
PD77115, 77115A
7. INSTRUCTIONS 7.1 Outline of Instructions
An instruction consists of 32 bits. Almost all the instructions, except some such as branch instructions, are executed with one system clock. The maximum instruction cycle of the PD77115 is 13.3 ns. The following nine types of instructions are available: (1) Trinomial operation instructions These instructions specify an operation by the MAC. As the operands, three general-purpose registers can be specified. (2) Binomial operation instructions These instructions specify an operation by the MAC, ALU, or BSFT. As the operands, two general-purpose registers can be specified. An immediate value can be specified for some of these instructions, instead of a general-purpose register, for one input. (3) Uninominal operation instructions These instructions specify an operation by the ALU. As the operands, one general-purpose register can be specified. (4) Load/store instructions These instructions transfer 16-bit values between memory and a general-purpose register. Any general-purpose register can be specified as the transfer source or destination. (5) Register-to-register transfer instructions These instructions transfer data from one general-purpose register to another. (6) Immediate value setting instructions These instructions write an immediate value to a general-purpose register and the registers of the address operation unit. (7) Branch instructions These instruction specify branching of program execution. (8) Hardware loop instructions These instruction specify repetitive execution of an instruction. (9) Control instructions These instructions are used to control the program.
Data Sheet U14867EJ5V0DS
25
PD77115, 77115A
7.2 Instruction Set and Operation
An operation is written in the operation field for each instruction in accordance with the operation representation format of that instruction. If two or more parameters can be written, select one of them. (a) Representation formats and selectable registers The following table shows the representation formats and selectable registers.
Representation Format r0, r0', r0" rI, rI' rh, rh' re reh dp dn dm dpx dpy dpx_mod dpy_mod dp_imm *xxx R0 to R7 R0L to R7L R0H to R7H R0E to R7E R0EH to R7EH DP0 to DP7 DN0 to DN7 DMX, DMY DP0 to DP3 DP4 to DP7 DPn, DPn++, DPn- -, DPn##, DPn%%, !DPn## (n = 0 to 3) DPn, DPn++, DPn- -, DPn##, DPn%%, !DPn## (n = 4 to 7) DPn##imm (n = 0 to 7) Contents of memory with address xxx If the contents of the DP0 register are 1000, *DP0 indicates the contents of address 1000 of the memory. Selectable Register
26
Data Sheet U14867EJ5V0DS
PD77115, 77115A
(b) Modifying data pointer The data pointer is modified after the memory has been accessed. The result of modification becomes valid starting from the instruction that immediately follows. The data pointer cannot be modified.
Example DPn DPn++ DPn- - DPn## Operation Nothing is done (value of DPn is not changed.) DPn DPn + 1 DPn DPn - 1 DPn DPn + DNn (Adds value of corresponding DN0 to DN7 to DP0 to DP7.) Example: DP0 DP0 + DN0 DPn%% (n = 0 to 3) DPn = ((DPL + DNn) mod (DMX + 1)) + DPH (n = 4 to 7) DPn = ((DPL + DNn) mod (DMY + 1)) + DPH !DPn## Reverses bits of DPn and then accesses memory. After memory access, DPn DPn + DNn DPn DPn + imm
DPn##imm
(c) Instructions that can be simultaneously written Instructions that can be simultaneously written are indicated by O. (d) Status of overflow flag (OV) The status of the overflow flag is indicated by the following symbol: * : Not affected
: Set to 1 when overflow occurs Caution If an overflow does not occur as a result of an operation, the overflow flag is not reset but retains the status before the operation.
Data Sheet U14867EJ5V0DS
27
PD77115, 77115A
Instruction Set
Instructions Simultaneously Written Instruction Instruction Name Mnemonic Operation
Trino- Bino- Unino- Load/ Transmial mial minal store fer Immediate value Branch Control
Flag
Loop
OV
Trinomial operation
Multiply add
ro = ro + rh * rh'
ro ro + rh * rh'
Multiply sub
ro = ro - rh * rh'
ro ro - rh * rh'
Sign unsign multiply add
ro = ro + rh * rl (rl is in positive integer format.)
ro ro + rh * rl
Unsign unsign multiply add
ro = ro + rl * rl' (rl and rl' are in positive integer format.)
ro ro + rl * rl'
1-bit shift multiply add
ro = (ro>>1) + rh * rh'
ro ro 2 + rh * rh'
16-bit shift multiply ro = (ro>>16) + rh * rh' add
ro ro 216 + rh * rh'

* *
Binomial operation
Multiply Add
ro = rh * rh' ro" = ro + ro'
ro rh * rh' ro" ro + ro'
Immediate add
ro' = ro + imm
ro' ro + imm (where imm 1)
Sub
ro" = ro - ro'
ro" ro - ro'
Immediate sub
ro' = ro - imm
ro' ro - imm (where imm 1)
Arithmetic right shift Immediate arithmetic right shift Logical right shift Immediate logical right shift Logical left shift Immediate logical left shift AND Immediate AND OR Immediate OR Exclusive OR Immediate exclusive OR
ro' = ro SRA rl
ro' ro >> rl ro' ro >> imm
* *
ro' = ro SRA imm
ro' = ro SRL rl ro' = ro SRL imm
ro' ro >> rl ro' ro >> imm ro' ro << rl ro' ro << imm ro" ro & ro' ro' ro & imm ro" ro ro' ro' ro imm ro" ro ro' ro' ro imm

* *
ro' = ro SLL rl ro' = ro SLL imm
* *
ro" = ro & ro' ro' = ro & imm ro" = ro ro' ro' = ro imm ro" = ro ro' ro' = ro imm

* *
* *
* *
28
Data Sheet U14867EJ5V0DS
PD77115, 77115A
Instructions Simultaneously Written Instruction Instruction Name Mnemonic Operation
Trino- Bino- Unino- Load/ Transmial mial minal store fer Immediate value Branch Control
Flag
Loop
OV *
Binomial operation
Less than
ro" = LT (ro, ro')
if (ro < ro') {ro" 0x0000000001} else {ro" 0x0000000000} ro 0x0000000000 ro' ro + 1
ro' ro - 1
if (ro < 0) {ro' -ro} else {ro' ro}
ro' ~ro ro' -ro
if ( ro > 0x007FFFFFFF) {ro' 0x007FFFFFFF} elseif {ro < 0xFF80000000} {ro' 0xFF80000000} else {ro' ro}
Uninominal operation
Clear Increment
Decrement
Absolute value
CLR (ro) ro' = ro + 1
ro' = ro - 1
ro' = ABS (ro)

*
1's complement 2's complement
Clip
ro' = ~ro ro' = -ro
ro' = CLIP (ro)

*
*
Round
ro' = ROUND (ro)
if (ro > 0x007FFF0000) {ro' 0x007FFF0000} elseif {ro < 0xFF80000000} {ro' 0xFF80000000} else {ro' (ro + 0x8000) & 0xFFFFFF0000}
1 ro' log2 ( ro)
*
Exponent
Substitution Accumulated addition
Accumulated subtraction
Division
ro' = EXP (ro)
ro' = ro ro' + = ro
ro' - = ro

* *
ro' ro ro' ro' + ro
ro' ro' - ro
ro' / = ro
if (sign (ro') == sign (ro)) {ro' (ro' - ro) << 1} else {ro' (ro' + ro)<<1} if (sign (ro')==0) {ro' ro' + 1}
Data Sheet U14867EJ5V0DS
29
PD77115, 77115A
Instructions Simultaneously Written Instruction Instruction Name Mnemonic Operation
Trino- Bino- Unino- Load/ Transmial mial minal store fer Immediate value Branch Control
Flag
Loop
OV *
Load/ store
Parallel load/store
Notes 1, 2
ro = *dpx_mod ro' =*dpy_mod ro = *dpx_mod *dpy_mod = rh *dpx_mod = rh ro = *dpy_mod *dpx_mod = rh *dpy_mod = rh'
ro *dpx, ro' *dpy ro *dpx, *dpy rh *dpx rh, ro *dpy *dpx rh, *dpy rh' dest *dpx, dest *dpy dest *dpx, *dpy source *dpx source, dest *dpy *dpx source, *dpy source' dest *addr *addr source dest *dp *dp source dest rl rl source rl imm dp imm dn imm dm imm
Partial load/ store
Notes 1, 2, 3
dest = *dpx_mod dest = *dpy_mod dest = *dpx_mod *dpy_mod = source *dpx_mod = source dest = *dpy_mod *dpx_mod = source *dpy_mod = source'
*
Direct addressing load/store
Note 4
dest = *addr *addr = source dest = *dp_imm *dp_imm = source dest = rl rl = source rl = imm (where imm = 0 to 0xFFFF) dp = imm (where imm = 0 to 0xFFFF) dn = imm (where imm = 0 to 0xFFFF) dm = imm (where imm = 1 to 0xFFFF)
*
Immediate value index load/store Registerto-register transfer Immediate value setting
Note 5
*
Register-toregister transfer
Note 6
*
Immediate value setting
*
Notes 1. Of the two mnemonics, either one of them or both can be written. 2. After transfer, modification specified by mod is performed. 3. Select any of dest, dest' = {ro, reh, re, rh, rl}, source, source' = {re, rh, rl}. 0: X-0xFFF : X (X memory) 4. Select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}, addr = . 0: Y-0xFFFF : Y (Y memory)
5. Select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}. 6. Select any register other than general-purpose registers as dest and source.
30
Data Sheet U14867EJ5V0DS
PD77115, 77115A
Instructions Simultaneously Written Instruction Instruction Name Mnemonic Operation
Trino- Bino- Unino- Load/ Transmial mial minal store fer Immediate value Branch Control
Flag
Loop
OV * * *
Branch
Jump Register indirect jump Subroutine call
JMP imm JMP dp
PC imm PC dp SP SP + 1 STK PC + 1 PC imm SP SP + 1 STK PC + 1 PC dp PC STK SP SP - 1 PC STK STK SP - 1 Recovery of interrupt enable flag RC count RF 0 During repeat End PC PC RC RC - 1 PC PC + 1 RF 1 RC count RF 0 During repeat End PC PC RC RC - 1 PC PC + 1 RF 1

CALL imm
Register indirect subroutine call Return
CALL dp
*
RET

* *
Interrupt return
RETI
Hardware loop
Repeat
REP count
Start
*
Loop
LOOP count (instruction of two or more lines)
Start
*
Loop pop
LPOP
LC LSR3 LE LSR2 LS LSR1 LSP LSP - 1 PC PC + 1 CPU stops. CPU, PLL, and OSC stop
*
Control
No operation Halt Stop
NOP HALT STOP
* * * * *
Condition Forget interrupt
IF (ro cond) FINT
Condition test Discard interrupt request
Data Sheet U14867EJ5V0DS
31
PD77115, 77115A
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25C)
Parameter Supply voltage Symbol IVDD EVDD Input voltage Output voltage Storage temperature Operating ambient temperature VI VO Tstg TA Condition For DSP core For I/O pins VI < EVDD + 0.5 V Rating -0.5 to +3.6 -0.5 to +4.6 -0.5 to +4.1 -0.5 to +4.1 -65 to +150 -40 to +85 Unit V V V V C C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions
Parameter Operating voltage Symbol IVDD EVDD Input voltage VI Condition For DSP core For I/O pins MIN. 2.0 2.7 0 TYP. MAX. 2.7 3.6 EVDD Unit V V V
Capacitance (TA = +25C, IVDD = 0 V, EVDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO Condition f = 1 MHz, Pins other than those tested: 0 V MIN. TYP. 10 10 10 MAX. Unit pF pF pF
32
Data Sheet U14867EJ5V0DS
PD77115, 77115A
DC Characteristics (Unless otherwise specified, TA = - 40 to + 85C, with IVDD and EVDD within recommended operating condition range)
Parameter High-level input voltage Symbol VIHN VIHS Condition Pins other than below RESET, INT1 to INT4, SCK, SIEN, SOEN VIHC CLKIN 0.5 EVDD +0.25 Low-level input voltage VIL VIC Pins other than below CLKIN IOH = -2.0 mA IOH = -100 A Low-level output voltage High-level input leakage current Low-level input leakage current Pull-up pin current Pull-down pin current Internal supply current [VIHN = VIHS = EVDD, VIL = 0 V, no load] IDDH IPUI IPDI IDD
Note
MIN. 0.7 EVDD 0.8 EVDD
TYP.
MAX. EVDD EVDD
Unit V V
EVDD
V
0 0
0.2 EVDD 0.5 EVDD -0.25
V V
High-level output voltage
VOH
0.7 EVDD 0.8 EVDD 0.2 EVDD 0 -10 -250 0 TBD 10
V V V
VOL ILH
IOL = 2.0 mA Other than TDI, TMS, and TRST VI = EVDD
A A A A
mA
ILL
Other than TDI, TMS, and TRST VI = 0 V TDI, TMS, 0 V VI EVDD TRST, 0 V VI EVDD During operating, 30 ns, IVDD = 2.7 V In halt mode, tcC = 30 ns, divided by eight, IVDD = 2.7 V
0
0 250 75
TBD
10
mA
IDDS
In stop mode, 0C < TA < 60C
100
A
Note The TYP. values are when an ordinary program is executed. The MAX. values are when a special program that brings about frequent switching inside the device is executed.
Data Sheet U14867EJ5V0DS
33
PD77115, 77115A
Common Test Criteria of Switching Characteristics
0.8 EVDD 0.5 EVDD 0.2 EVDD 0.8 EVDD 0.5 EVDD 0.2 EVDD
RESET, INT1 to INT4, SCK, SIEN, SOEN
Test points
CLKIN
0.5 EVDD+0.25 0.5 EVDD 0.5 EVDD-0.25
Test points
0.5 EVDD+0.25 0.5 EVDD 0.5 EVDD-0.25
Input (other than above)
0.7 EVDD 0.5 EVDD 0.2 EVDD
Test points
0.7 EVDD 0.5 EVDD 0.2 EVDD
Output
0.5 EVDD
Test points
0.5 EVDD
34
Data Sheet U14867EJ5V0DS
PD77115, 77115A
AC Characteristics (TA = - 40 to + 85C, with IVDD and EVDD within recommended operating condition range) Clock Timing requirements
Parameter CLKIN cycle time
Note 1
Symbol tcCX
Condition
MIN. 25
TYP.
MAX.
Unit ns
PLL lock range
Note 2
IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V
15 x m 10 x m
50 x m 50 x m
ns
ns
CLKIN high-level width CLKIN low-level width CLKIN rise/fall time Internal clock cycle time requirements
Note 3
twCXH twCXL trfCX tcC (R) IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V
12.5 12.5 5 20 13.3
ns ns ns ns ns
Notes 1. m: Multiple 2. This is the range in which the PLL is locked (stably oscillates). Input tcCX within this range. 3. Input tcCX so that the value of (tcCX / m x n) satisfies this condition. m: Multiple, n: Division ratio Switching characteristics
Parameter Internal clock cycle
Note
Symbol tcC
Condition External clock operation PLL clock operation In HALT mode
MIN.
TYP. tcCX (tcCX / m) x n (tcCX / m) x n x l tcC
MAX.
Unit ns ns ns ns ns ns
CLKOUT cycle time CLKOUT width
tcCO twCO During normal operation n = 1, or even number n = odd number (other than 1) tcC / n - 3 tcC / 2 - 3 tcC / n - 3
In HALT mode CLKOUT rise/fall time CLKOUT delay time trfCO tdCO IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V
ns 5 20 15 ns ns ns
Note m: Multiple, n: Division ratio, l: HALT division ratio
Data Sheet U14867EJ5V0DS
35
PD77115, 77115A
Clock I/O timing
tcCX twCXH twCXL trfCX trfCX
CLKIN
tcC, tcC(R)
Internal clock
tcCO tdCO twCO twCO trfCO trfCO
CLKOUT
36
Data Sheet U14867EJ5V0DS
PD77115, 77115A
Reset, Interrupt Timing requirements
Parameter RESET low-level width WAKEUP low-level width INT1 to INT4 low-level width INT1 to INT4 recovery time Symbol tw (RL) tw (WAKEUPL) tw (INTL) trec (INT) Condition MIN. 6 tcC
Note
TYP.
MAX.
Unit ns
6 tcC 3 tcC
Note
s
ns ns
3 tcC
Note
Note that tcC is I (I = integer of 1 to 16) times that during normal operation in the HALT mode.
Reset timing
tw(RL)
RESET
WAKEUP timing
tw (WAKEUPL)
WAKEUP
Interrupt timing
trec(INT)
tw(INTL)
INT1 to INT4
Data Sheet U14867EJ5V0DS
37
PD77115, 77115A
Serial Interface (Audio Serial mode) Timing requirements
Parameter MCLK cycle time MCLK high-/low-level width MCLK rise/fall time BCLK cycle time BCLK high-/low-level width BCLK rise/fall time LRCLK setup time SI setup time SI hold time Symbol tcMC twMC trfMC tcBC twBC trfBC tsu(BC-LR) tsuSI thSI Condition Master mode Master mode Master mode Slave mode Slave mode Slave mode Slave mode 50 50 50 300 120 20 MIN. 40 0.4 x tcMC Note TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
Note 5 or maximum value of 0.1 x tcMC Switching characteristics
Parameter BCLK cycle time Symbol tcBC Condition Master mode, 64-bit mode Master mode, 32-bit mode BCLK high-/low-level width BCLK rise/fall time LRCLK delay time SO output delay time twBC trfBC td(BC-LR) tdSO Master mode Master mode Master mode -40 -40 0.4 tcBC 20 +40 +40 MIN. TYP. 1/64 fs 1/32 fs MAX. Unit ns ns ns ns ns ns
38
Data Sheet U14867EJ5V0DS
PD77115, 77115A
Audio Serial clock timing
tcMC twMC twMC trfMC trfMC
MCLK
Audio Serial Master mode timing
tcBC twBC twBC
trfBC
trfBC
BCLK (OUTPUT)
td(BC-LR) LRCLK (OUTPUT)
tdSO SO
tsuSI
td(BC-LR)
thSI
SI
Audio Serial Slave mode timing
tcBC twBC twBC
trfBC
trfBC
BCLK (INPUT)
tsu(BC-LR) LRCLK (INPUT)
tdSO SO
tsuSI
tsu(BC-LR)
thSI
SI
Data Sheet U14867EJ5V0DS
39
PD77115, 77115A
Serial Interface (Standard Serial mode) Timing requirements
Parameter SCK cycle time SCK high-/low-level width SCK rise/fall time SOEN setup time Symbol tcSC twSC trfSC tsuSOE IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V SOEN hold time thSOE IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V SIEN setup time tsuSIE IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V SIEN hold time thSIE IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V SI setup time tsuSI IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V SI hold time thSI IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V 10 5 15 10 10 5 15 10 10 5 15 10 Condition MIN. 60 and 2tcC 25 20 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Switching characteristics
Parameter SO output delay time Symbol tdSO Condition IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V SO hold time thSO 0 MIN. TYP. MAX. 30 25 Unit ns ns ns
40
Data Sheet U14867EJ5V0DS
PD77115, 77115A
Serial output timing 1
tcSC twSC twSC
trfSC
trfSC
SCK
tsuSOE tsuSOE thSOE thSOE SOEN tdSO
Hi-Z
tdSO 1st Last
thSO
SO
Serial output timing 2 (during successive output)
tcSC twSC twSC
trfSC
trfSC
SCK
tsuSOE thSOE SOEN tdSO
Last
thSO
SO
1st
Last
Data Sheet U14867EJ5V0DS
41
PD77115, 77115A
Serial input timing 1
tcSC twSC SCK tsuSIE tsuSIE thSIE SIEN thSIE twSC
trfSC trfSC
tsuSI SI
1st
thSI
2nd
3rd
Serial input timing 2 (during successive input)
tcSC twSC SCK tsuSIE thSIE SIEN tsuSI thSI twSC
trfSC trfSC
SI
Last-1
Last
1st
2nd
3rd
42
Data Sheet U14867EJ5V0DS
PD77115, 77115A
Caution If noise is superimposed on the serial clock, the serial interface may be deadlocked. Bear in mind the following points when designing your system: * Reinforce the wiring for power supply and ground (if noise is superimposed on the power and ground lines, it has the same effect as if noise were superimposed on the serial clock). * Shorten the wiring between the device's SCK pin, and clock supply source. * Do not cross the signal lines of the serial clock with any other signal lines. Do not route the serial clock line in the vicinity of a line through which a high alternating current flows. * Supply the clock to the SCK pin of the device from the clock source on a one-to-one basis. Do not supply clock to several devices from one clock source. * Exercise care that the serial clock does not overshoot or undershoot. In particular, make sure that the rising and falling of the serial clock waveform are clear.
x Make sure that the serial clock rises and falls linearly. The serial clock must not bound. Noise must not be superimposed on the serial clock.
x The serial clock must not rise or fall step-wise.
Data Sheet U14867EJ5V0DS
43
PD77115, 77115A
Host Interface Timing requirements
Parameter HRD delay time Symbol tdHR Condition IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V HRD width HCS, HA0, HA1, read hold time HCS, HA0, HA1 write hold time HRD, HWR recovery time HWR delay time trecHS tdHW IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V HWR width HWR hold time HWR setup time twHW thHDW tsuHDW IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V 3tcC 15 10 40 0 15 10 ns ns ns ns ns ns ns thHCAW 0 ns twHR thHCAR MIN. 15 5 40 0 TYP. MAX. Unit ns ns ns ns
Switching characteristics
Parameter HRE, HWE output delay time Symbol tdHE Condition IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V HRE, HWE hold time thHE IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V HRD valid time tvHDR IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V HRD hold time thHDR 0 MIN. TYP. MAX. 30 25 30 25 30 25 Unit ns ns ns ns ns ns ns
44
Data Sheet U14867EJ5V0DS
PD77115, 77115A
Host read interface timing
CLKIN
HCS, HA0, HA1
thHCAR
tdHR twHR
trecHS
HRD
thHDR
Hi-Z
tvHDR
HD0 to HD15
Hi-Z
tdHE
thHE
HRE
Host write interface timing
CLKIN
HCS, HA0, HA1
thHCAW tdHW twHW trecHS
HWR
thHDW
tsuHDW
HD0 to HD15
tdHE
thHE
HWE
Data Sheet U14867EJ5V0DS
45
PD77115, 77115A
General-purpose I/O Port Timing requirements
Parameter Port input setup time Port input hold time Symbol tsuPI thPI IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V Condition MIN. 0 15 10 TYP. MAX. Unit ns ns ns
Switching characteristics
Parameter Port output delay time Symbol tdPO Condition IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V MIN. TYP. MAX. 30 25 Unit ns ns
General-purpose I/O port timing
CLKIN
tdPO P0 to P7 (Output) tsuPI thPI
P0 to P7 (Input)
46
Data Sheet U14867EJ5V0DS
PD77115, 77115A
SD card Interface Timing requirements
Parameter SDCR input setup time SDCR input hold time SDDAT input setup time SDDAT input hold time Symbol tsuSDCR thSDCR tsuSDD thSDD Condition Input Response Input Response Input data Input data MIN. 5 0 5 0 TYP. MAX. Unit ns ns ns ns
Switching characteristics
Parameter SDCLK cycle time SDCLK high- level width SDCLK low-level width SDCLK rise/fall time SDCR output delay time SDCR output valid time SDDAT output delay time SDDAT output valid time Symbol tcSDC twSDCH twSDCL trfSDC tdSDCR tvSDCR tdSDD tvSDD Output Command Output Command Output data Output data 0 0 10 Condition MIN. 40 10 10 10 10 TYP. MAX. Unit ns ns ns ns ns ns ns ns
Data Sheet U14867EJ5V0DS
47
PD77115, 77115A
SDCR timing
tcSDC
twSDCL twSDCH
trfSDC trfSDC
SDCLK
tdSDCR SDCR (Output) tsuSDCR thSDCR
SDCR (Input)
tvSDCR
SDDAT timing
tcSDC
twSDCL twSDCH
trfSDC trfSDC
SDCLK
tdSDD SDDAT (Output) tsuSDD thSDD
SDDAT (Input)
tvSDD
48
Data Sheet U14867EJ5V0DS
PD77115, 77115A
Debugging Interface (JTAG) Timing requirements
Parameter TCK cycle time TCK high-/low-level width TCK rise/fall time TMS, TDI setup time Symbol tcTCK twTCK trfTCK tsuDI IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V TMS, TDI hold time thDI IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V Input pin setup time tsuJIN IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V Input pin hold time thJIN IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V TRST setup time tsuTRST 25 20 25 20 25 20 25 20 100 Condition MIN. 120 50 20 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
Switching characteristics
Parameter TDO output delay time Symbol tdDO Condition IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V Output pin output delay time tdJOUT IVDD = 2.0 to 2.7 V IVDD = 2.3 to 2.7 V MIN. TYP. MAX. 25 20 25 20 Unit ns ns ns ns
Data Sheet U14867EJ5V0DS
49
PD77115, 77115A
Debugging interface timing
tcTCK twTCK twTCK trfTCK trfTCK
TCK
tsuTRST
TRST
tsuDI thDI
TMS, TDI
Valid
Valid
Valid
tdDO
TDO
tsuJIN thJIN
Capture state
Valid
tdJOUT
Update state
Remark For details of JTAG, refer to IEEE1149.1.
50
Data Sheet U14867EJ5V0DS
PD77115, 77115A
9. PACKAGES
80-PIN PLASTIC FBGA (9x9)
D
wSA
ZE
ZD
A
B E
9 8 7 6 5 4 3 2 1 JHGFEDCBA
INDEX MARK
wSB
A y1 S A2
(UNIT:mm)
S
ITEM D E w
DIMENSIONS 9.000.10 9.000.10 0.20 1.280.10 0.350.06 0.93 0.80 0.50 +0.05 -0.10 0.08 0.10 0.20 1.30 1.30 P80F1-80-CN6
y
S
e
A1
M
A A1 A2 e b x y y1 ZD ZE
b
x
S AB
Data Sheet U14867EJ5V0DS
51
PD77115, 77115A
80-PIN PLASTIC TQFP (FINE PITCH) (12x12)
A B
60
61
41 40
detail of lead end S C D Q R
80 1 20
21
F G H P I
M
J
K
S
N
NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
S
L M
ITEM A B
C
MILLIMETERS 14.00.2 12.00.2
12.00.2
D
F
14.00.2
1.25
G
H I
1.25
0.220.05 0.10 0.5 (T.P.) 1.00.2
0.50.2
J
K
L
M
N P
0.1450.05
0.10 1.00.05 0.10.05
3 +7 -3
Q
R
S
1.2 MAX. S80GK-50-9EU-1
52
Data Sheet U14867EJ5V0DS
PD77115, 77115A
10. RECOMMENDED SOLDERING CONDITIONS
It is recommended to solder this product under the following conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Surface-Mount Type * PD77115GK-9EU: 80-pin plastic TQFP (fine-pitch) (12 x 12)
Soldering Process Infrared ray reflow Soldering Conditions Package peak temperature: 235C, Time: 30 seconds MAX (210C MIN), Number of times: 2 MAX, Number of days: 3Note (after that, prebaking is necessary for 10 to 72 hours at 125C)) VPS Package peak temperature: 215C, Time: 40 seconds MAX (200C MIN), Number of times: 2 MAX, Number of days: 3Note (after that, prebaking isnecessary for 10 to 72 hours at 125C) Partial heating method Pin temperature: 300C MAX, Time: 3 seconds MAX (per side of device) - VP15-103-2 Symbol IR35-103-2
* PD77115F1-CN6: 80-pin plastic FBGA (9 x 9) * PD77115AF1-xxx-CN6: 80-pin plastic FBGA (9 x 9)
Soldering Process Infrared ray reflow Soldering Conditions Package peak temperature: 235C, Time: 30 seconds MAX (210C MIN), Number of times: 2 MAX, Number of days: 3Note (after that, prebaking is necessary for 10 to 72 hours at 125C)) VPS Package peak temperature: 215C, Time: 40 seconds MAX (200C MIN), Number of times: 2 MAX, Number of days: 3Note (after that, prebaking isnecessary for 10 to 72 hours at 125C) VP15-103-2 Symbol IR35-103-2
Note Number of days in storage after the dry pack has been opened. The storage conditions are at 25C, 65% RH MAX. Caution Apply wave soldering only to the pins and be careful not to bring solder into direct contact with the package.
Data Sheet U14867EJ5V0DS
53
PD77115, 77115A
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html
NEC Electronics America, Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782
NEC Electronics (Europe) GmbH
Duesseldorf, Germany Tel: 0211-65030
* Sucursal en Espana
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318
NEC Electronics Hong Kong Ltd.
Seoul Branch Seoul, Korea Tel: 02-558-3737
Madrid, Spain Tel: 091-504 27 87
* Succursale Francaise
Velizy-Villacoublay, France Tel: 01-30-67 58 00
* Filiale Italiana
NEC Electronics Shanghai Ltd.
Shanghai, P.R. China Tel: 021-5888-5400
Milano, Italy Tel: 02-66 75 41
* Branch The Netherlands
NEC Electronics Taiwan Ltd.
Taipei, Taiwan Tel: 02-2719-2377
Eindhoven, The Netherlands Tel: 040-244 58 45
* Tyskland Filial
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 6253-8311
Taeby, Sweden Tel: 08-63 80 820
* United Kingdom Branch
Milton Keynes, UK Tel: 01908-691-133
J04.1
54
Data Sheet U14867EJ5V0DS
PD77115, 77115A
NOTES FOR CMOS DEVICES
1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.
Data Sheet U14867EJ5V0DS
55
PD77115, 77115A
These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited.
* The information in this document is current as of August, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

▲Up To Search▲

Price & Availability of UPD77115AF1-XXX-CN6

	To Download UPD77115AF1-XXX-CN6 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .